1. Field of the Invention
This invention relates generally to apparatus and process for manufacturing integrated circuits (ICs) on semiconductor wafers. More particularly, this invention relates to a novel alignment technique for aligning a semiconductor wafer with a mask or a reticle by employing an optical system which can detect the relative positions of the alignment marks disposed on the backside of the semiconductor wafer with respect to the alignment marks on a mask or a reticle to be aligned thereto.
2. Description of the Prior Art
As higher alignment precision is required for integrated circuit (IC) manufacture to produce ICs with ever shrinking line widths operated at higher speed while providing greater degree of functional integration, the difficulties to accurately and clearly detect and measure the positions of the alignment marks on a wafer often become a limitation to further miniaturize the IC devices. The difficulties arise from the fact the alignment marks on a wafer employed for relative position measurements are often smeared or stained as the results of various manufacturing processes. As the alignment marks become blurred and not clearly distinguishable, an alignment measurement may not be accurately performed. Specifically, the sharp and fine lines of the alignment marks may become blemished and indefinite when a planarization process is applied over the top surface of the wafer including the surface areas of these marks. The planarization step is commonly carried out by applying a chemical and mechanical polishing (CMP) process. As the CMP process is applied to the alignment marks, the fine line definition of the alignment marks may be lost and no longer suitable for the purpose of high precision alignment. Additionally, in the process of forming various circuit elements, various layers are formed over the top surface and then patterned. These process may also cause the alignment marks to become blurred and unclear thus causing difficulties and imprecision in detecting these marks for position measurement.
FIG. 1 is a functional block diagram showing the alignment system commonly employed in a conventional IC manufacturing process. The alignment system 10 includes a light source 15 for projecting an alignment beam 20 to a beam splitter 25. The alignment beam 20 is spitted into two beams with a first beam 20-1 projecting to a reticle 30 with a set of reticle alignment marks 35 formed thereon. The first alignment beam 20-1 transmitted through the reticle alignment marks and the quartz portion 30-1 of the reticle 30 to reach an alignment detector 40. In the meantime, a second alignment beam 20-2 is reflected by the beam splitter 25 to a wafer 45 supported on a wafer chuck 50. As shown in FIG. 1, the wafer includes a substrate 45-3 which has a set of wafer alignment marks 60 formed on the top surface of the substrate 45-3. The substrate 45-3 of the wafer 45 is covered by a CMP oxide layer 45 and also by a metal layer 45-1. The oxide layers 45 is transparent to allow the alignment beam 20-2 to reach the alignment marks 60 on the top surface of the substrate 45-3. The metal layer 45-1 is however not transparent to the alignment beam. Under the circumstance when a CMP process is not performed, the alignment operation would still be feasible because the alignment marks 60 on the substrate 45-3 are transferred to the metal layer 45-1. The alignment beam 25-2 is then reflected from the top surface of the substrate 45-3 and transmitted through the CMP oxide layer 45-2 and the metal layer 45-1, or directly from the alignment marks transferred to the top surface of the metal layer 45-1, to reach the alignment detector 40. The alignment beams 20-1 and 20-2 received by the alignment detector are then employed to determine the relative position of the wafer 45 relative to the reticle 30. Based the results of the relative position analysis, the position of the wafer is then adjusted by moving the wafer chuck 50 to assure precise alignment of the wafer 45 with the reticle 30. However, when a CMP process is carried out, the top surface of the metal layer 45-1 is polished thus the alignment marks which are transferred to the metal layer surface are no longer visible. A failure of the alignment operation occurs due to the fact the metal layer 45-1 blocks the alignment beam.
As discussed above, there are several ways that the alignment marks 60 on the top surface of the substrate 45-3 may become obscure and not suitable for high precision alignment operation. Specifically, since a CMP planarization process is often applied to the top surface, the marks maybe polished and become smeared and the fine lines of the marks may be spread thus unsuitable for alignment to be conducted with thin lines of very fine resolution. Furthermore, the wafer alignment marks 60 in some cases are covered by the CMP oxide layer 45-2. When the CMP oxide layer 45-2 is not formed with flat and uniform layer thickness, the optical path of the alignment beam 20-2 may be deviated from the straight line between the splitter 25 and the wafer alignment marks 60. The alignment is distorted due to this optical path deviation. Additionally, since the alignment marks 60 are covered under various layers, e.g., the oxide layer 45-2 and the metal layer 45-1, the beam intensity may be reduced as the light flux is annihilated by these different layers. Also, the wafer alignment marks 60, when covered below these layers may often become indefinite and unclear. Poor light quality is usually generated from the reflection of the alignment beam 20-2 from the top surface of the substrate 45-3 formed with the wafer alignment marks thereon. All these factors may adversely affect the quality and precision of the alignment process.
Suzuki discloses in U.S. Pat. No. 5,048,968, entitled "Alignment Mark Detecting Optical System" (issued Sep. 17, 1991), an alignment mark detecting optical system which is usable with an automatic alignment apparatus. The alignment marks of a wafer and a mask are scanned by a laser beam to detect the state of misalignment between these two sets of marks. The laser beam scans the surface of the wafer opposed to the mask and the surface of the mask opposed to the wafer, i.e., the front face of the wafer and the back face of the mask. The light beams reflected by the surfaces are introduced to one or more photo detectors. As pointed out in the patent, this alignment system provides the advantage that it can be used with an automatic alignment system and provide highly efficient operation. However, this system does not provides a solution to the difficulty that the alignment marks may become smeared due to the polishing process carried out over the surface facing the masks or the alignment beam may be obscured by the overlying layers covering the alignment marks.
A "step and repeat" type of reduction projection exposure apparatus is disclosed in U.S. Pat. No. 4,952,060 where the light sources are employed to project light beams, in two different steps, on the alignment marks of the wafer and then on the alignment marks of the reticle. The alignment system includes optical elements used for two steps, i.e., "step and repeat" alignment operation. The reticle is first aligned with a set of reference points, with the wafer removed, by a reticle alignment beam. Then this set of common reference points are employed for alignment of the wafer by applying a separate wafer alignment beam on the backside of the wafer. However, since two separate beams from two separate light sources and two separate steps are involved in the alignment, in addition to the trouble of carefully aligning the optical system with these two set of light sources, the accuracy of the alignment is also affected due to the fact the there is no comparison and matching of light beams from direct single beam alignment. The indirect relative position alignment with a set of common reference points as disclosed in this patent may not be suitable for high precision application due to the fact that it involves additional imprecision when a two step process is applied. Furthermore, the through-put of wafer production is reduced due to the additional alignment step.
Therefore, a need still exists in the art of integrated circuit manufacture to overcome this difficulty. The improved process must provide direct and precise alignment whereby the method can be applied for high precision manufacture requirements. Furthermore, it is preferable that the method can be conveniently employed without requiring complicate optical path arrangements such that calibration alignment of the optical system can be conveniently completed without time consuming process and a low production cost can be maintained.